module data_trunc (
  input  [63:0] rw_rdata,
  input  [63:0] alu,
  input  [2:0]  memdata_width,
  output wire [63:0] mem
);
reg [63:0] memreg;
reg [5:0] offset;
assign mem = memreg;
always @(*) begin
    offset = {3'b0,alu[2:0]} *8 ;
    case (memdata_width)
        3'b000:  memreg = 64'h00000000;    //不访存
        3'b001:  memreg = rw_rdata;    //double word
        3'b010:  memreg = {{32{rw_rdata[offset+31]}},rw_rdata[offset+:32]};    //word
        3'b011:  memreg = {{48{rw_rdata[offset+15]}},rw_rdata[offset+:16]};    //half word
        3'b100:  memreg = {{56{rw_rdata[offset+7]}},rw_rdata[offset+:8]};    //byte
        3'b101:  memreg = {32'b0,rw_rdata[offset+:32]};    //unsigned word
        3'b110:  memreg = {48'b0,rw_rdata[offset+:16]};    //unsigned half word
        3'b111:  memreg = {56'b0,rw_rdata[offset+:8]};    //unsigned byte
    endcase
end
endmodule